One major characteristic of a CMOS image sensor is that various functional circuits can be integrated on the image sensor, and one such functional circuit to be integrated is an A/D converter circuit. By this, a digital output image sensor can be integrated and the system can be compact, and also the influence of noise that enters the output of the sensor chip can be eliminated.
An A/D converter to be integrated on an image sensor is disclosed in the following documents.    [1] A. Simoni, A. Sartori, M. Gottaidi, A. Zorat: “A digital vision sensor”, Sensors and Actuators, A46–47, pp. 439–443, 1995    [2] B. Mansoorian, H. Y. Yee, S. Huang, E. Fossum: “A 250 mW 60 frames/s 1280×720 pixel 9b CMOS digital image sensor”. Dig. Tech. Papers, Int. Solid-State Circuits Conf., pp. 312–313, 1999    [3] T. Sugiki, S. Ohsawa, H. Miura, M. Sasaki, N. Nakamura, I. Ioune, M. Hoshino, Y. Tomizawa, T. Arakawa: “A 60 mW 10b CMOS imaging sensor with column-to-column FPN reduction”, Dig. Tech. Papers, Int. Solid-State Circuits Conf., pp. 108–109, 2000    [4] S. Decker, R. D. McGrath, K. Bremer, C. G. Sodini: “A 256×256 CMOS image array with wide dynamic range pixels and column-parallel digital output”, IEEE J. Solid-State Circuits, Vol. 33, No. 12, December 1998    [5] Japanese Patent Application Laid-Open No. 2002-232291
The above-mentioned “A digital vision sensor” discloses a technology for integrating 8-bit integral type A/D converter elements using a lamp signal generator, comparator and register in columns. A similar technology is also disclosed in “DESCRIPTION” of U.S. Pat. No. 2,532,374.
The above-mentioned “A 60 mW 10b CMOS imaging sensor with column-to-column FPN reduction” also discloses a technology for integrating the integral type A/D converter elements in columns, and 10-bit elements are implemented using a comparator of which accuracy has been improved. For these integral type A/D converters, it is difficult to implement a higher resolution since the conversion time is long, and particularly increasing resolution makes the conversion time longer exponentially. However linearity is superb.
The above-mentioned “A 250 mW 60 frames/s 1280×720 pixel 9b CMOS digital image sensor” discloses a technology for arranging successive approximation type A/D converters using a capacitor in columns so as to operate, which is appropriate for image sensors with a high frame rate and many pixels, since high-speed A/D conversion is possible. However the actual precision still remains around 8 bits.
The above-mentioned “A 256×256 CMOS image array with wide dynamic range pixels and column-parallel digital output” discloses a technology for arranging the cyclic A/D converter elements in columns so as to operate, which is also suitable for high-speed A/D conversion. However the resolution is about 9 bits.
The above-mentioned Japanese Patent Application Laid-Open No. 2002-2322915 discloses a technology for performing 2-stage integral type A/D conversion on signals of which noise is cancelled in columns, but this is not for improving the signal noise ratio (SNR) by 2-stage conversion, since the amplification function is not included.
In addition to the above, a few image sensors having A/D conversion elements within the pixel have been reported, but are omitted here since they are not directly related to the present invention.